In a CMOS image sensor, reset is performed to remove excess charge from a photoelectric conversion device, an electronic shutter operates to cause the photoelectric conversion device to store charge, and the stored charge is outputted as voltage signal to a vertical signal line. Now, the main part of a conventional CMOS image sensor and the operation thereof is briefly described below with reference to FIGS. 13 and 14.
FIG. 13 is an equivalent circuit diagram of the main part showing an example of configuration of the conventional CMOS image sensor.
FIG. 14 is a timing chart of the CMOS image sensor shown in FIG. 13. FIG. 14(A) shows a drive signal SDRN. FIG. 14(B) shows a reset signal SRST. FIG. 14(C) shows a transfer signal STRN.
A pixel circuit 30 of a CMOS image sensor 3 shown in FIG. 13 is placed in a pixel section 311. The pixel circuit 30 includes a transfer transistor 32, a reset transistor 33 and an amplifier transistor 34, and is driven by a row drive circuit 37. The pixel circuit 30 configured as shown in FIG. 13 is referred to as “3-transistor-driven pixel circuit,” “3-transistor-driven CMOS image sensor” or the like.
The row drive circuit 37 includes a transistor 39 for applying the drive signal SDRN of a low-level voltage VL to a drive signal line 310, and a transistor 38 for applying the drive signal SDRN of a high-level voltage VH to the drive signal line 310. The high-level voltage VH is, for example, a source voltage VDD, and the low-level voltage VL is a voltage for holding the amplifier transistor 34 in off-state.
When the pixel circuit 30 is a 3-transistor-driven pixel circuit, the row drive circuit 37 applies a binary voltage of the low-level voltage VL or high-level voltage VH to the drive signal line 310 to drive the pixel circuit 30.
During a period from time t1 to time t4, the row drive circuit 37 applies a gate voltage VL to the gate of the transistor 38 to hold only the transistor 38 in on-state and apply the drive signal SDRN of the high-level voltage VH to the drive signal line 310 (see FIG. 14(A)).
Before a photoelectric conversion device 31 starts to read charge (time t2), the row drive circuit 37 applies a pulse of the reset signal SRST to a reset signal line RSTL connected to the gate of the reset transistor 33 (see FIG. 14(B)). This resets the potential of a floating diffusion FD to the high-level voltage VH.
At time t3, the row drive circuit 37 applies a pulse of the transfer signal STRN to a transfer signal line TRNL connected to the gate of the transfer transistor 32 (see FIG. 14(C)). This transfers the charge stored by the photoelectric conversion device 31 to the floating diffusion FD.
At this point, the amplifier transistor 34 has the potential of the floating diffusion FD applied at the gate, and has the high-level voltage VH applied at the drain. Accordingly, the amplifier transistor 34 amplifies the potential of the floating diffusion FD depending on the voltage between the source and the gate, and outputs the amplified potential as voltage signal to a vertical signal line 35. The outputting of voltage signal from the amplifier transistor 34 is referred to as “the reading-out of charge,” “the reading-out of pixel” or the like, and is continued until time t4.
After reading out the charge, during a period from time t4 to time t5, the row drive circuit 37 holds only the transistor 39 in on-state to apply the drive signal SDRN of the low-level voltage VL to the drive signal line 310 (see FIG. 14(A)), and applies a pulse of the reset signal SRST to the reset signal line RSTL (see FIG. 14(B)).
After the low-level voltage VL is applied to the gate of the amplifier transistor 34 (floating diffusion FD), the reset signal SRST returns to the low-level voltage VL.
This holds the amplifier transistor 34 in off-state, causing the pixel circuit 30 to be in non-selected state in which outputting voltage signal is stopped, which completes the operation of the CMOS image sensor 3 in one horizontal period H.
As described above, when the charge is read out, the voltage signal from the pixel circuit 30 is applied to the vertical signal line 35, causing the potential of the vertical signal line 35 to change.
At this point, even if the number of pixel circuits 30 in non-selected state is small, when the pixel circuits 30 in non-selected state output voltage signals to the vertical signal line 35, these voltage signals are superimposed on voltage signals outputted from pixel circuits 30 of a read-out row. Consequently, the output voltages from the pixel circuits have an effect on the whole pixel area, causing various noises including shading.
These phenomena are closely related to how the drive signal SDRN falls at time t4. The more steeply the drive signal SDRN falls (see FIG. 14), the more intensely the potentials of the p-type wells of transistors included in the pixel circuit 30 fluctuate, causing phenomena including shading.
Thus, a method for reducing phenomena including shading by using a multivalued drive signal SDRN having different voltage levels and falling more gently is disclosed (see Patent Documents 1, 2).